1. Field of the Invention
The present invention relates to a bus connecting device, a bus connecting method, and a bus connecting program, and more particularly, to a bus connecting device, a bus connecting method, and a bus connecting program that can shorten an initial configuration time without changing software of a host.
This application is based upon and claims the benefit of priority from Japanese patent application No. 2007-101026, filed on Apr. 6, 2007, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
In the PCI express, a bus connecting device is used as a PCI Express switch which connects a host bridge included in a CPU or a host bridge arranged on a motherboard to a plurality of input and output (I/O) devices.
An example of the PCI Express switch is described in “PCI Express Base Specification Revision 1.1, PSI-SIG, on Mar. 28, 2005, pp. 34”. With reference to FIG. 1, a PCI Express switch will be described below.
The PCI Express switch 111 includes an upstream PCI-PCI bridge 1112, downstream PCI-PCI bridges 1114-1 to 1114-3, and an internal bus 1113.
The upstream PCI-PCI bridge 1112 stores a link connected to a host bridge. The downstream PCI-PCI bridges 1114-1 to 1114-3 store a link connected to an I/O device.
The internal bus 1113 connects the upstream PCI-PCI bridge 1112 to each of the downstream PCI-PCI bridges.
In the topology of the PCI Express, a CPU side is called an upstream side, and an I/O side is a downstream side.
In the PCI Express switch 111, an interface corresponding to the upstream PCI-PCI bridge 1112 is an upstream port 1111.
Interfaces corresponding to the downstream PCI-PCI bridges 1111-1 to 1114-3 are downstream ports 1115-1 to 1115-3.
The upstream PCI-PCI bridge 1112 and the downstream PCI-PCI bridges 1114-1 to 1114-3 include PCI Express configuration registers 11121-1 to 11121-4, respectively. The PCI Express configuration registers 11121-1 to 11121-4 hold bridge configuration information and accept device operations from a host.
A TLP (Transaction Layer Packet) serving as a packet for an I/O device received by the upstream PCI-PCI bridge 1112 is transferred to the I/O device through the downstream PCI-PCI bridge connected to a corresponding destination I/O in the downstream PCI-PCI bridge 1114-1 to 1114-3.
On the other hand, TLPs received by the downstream PCI-PCI bridges 1114-1 to 1114-3 and addressed to a host bridge are integrated to the upstream PCI-PCI bridge 1112 and transferred to the host bridge.
As another technique applied to a PCI device, a method that copes with various products by using a common device is proposed in JP-A-2003-330875 (page 6, FIG. 3). The PCI is a bus specification standardized before the PCI express.
FIG. 2 shows a PCI device 122 described in JP-A-2003-330875. The PCI device 122 includes a bus slave 1221 connected to a PCI bus 121 and three functions.
The functions include PCI card bus bridge slots 1222-1 and 1222-2, and an IEEE1394 interface 1223, respectively.
Function number 0 is allocated to the PCI card bus bridge slot 1222-1. Function number 1 is allocated to the PCI card bus bridge slot 1222-2. Function number 2 is allocated to the IEEE1394 interface 1223.
The functions holds PCI configuration registers 12221-1 to 12221-3, respectively.
A host is prohibited from accessing the PCI configuration registers 12221-1 to 12221-3 as needed, the corresponding function can be hidden from the host.
For example, the IEEE1394 interface 1223 corresponding to function 2 is hidden from the host, so that the PCI device 122 can act as if to be a device having functions 0 and 1.
Setting of accesses to the PCI configuration registers 12221-1 to 12221-3 is performed by changing the setting of the PCI configuration registers 12221-1 to 12221-3 of the next function or arranging a physical control pin outside the PCI device 122.
According to the method, even though a common device is used, depending on products, necessary functions are made valid for the products, respectively, and unnecessary functions are hidden to make it possible to customize the device functions and to reduce the number of types of devices.
The PCI Express switch 111 is combined to the technique related to the PCI device 122 described in JP-A-2003-330875 (page 6, FIG. 3) to make it possible to initially configure a downstream PCI-PCI bridge coupled to a I/O device in downstream PCI-PCI bridges 1114-1 to 1114-3 on the basis of the I/O connections of the downstream ports 1115-1 to 1115-3of the PCI Express switch 111 and to reduce an initial configuration time for the PCI Express switch 111 serving as a host.
More specifically, for a downstream port connected to an I/O device in the downstream ports 1115-1 to 1115-3, the host is permitted to access to the PCI Express configuration resister of the corresponding downstream bridge on the downstream port to show the presence of a bridge.
On the other hand, with respect to a downstream port which is not connected to an I/O device in the downstream ports 1115-1 to 1115-3, the host is prohibited from accessing the PCI Express configuration register on the downstream port to hide the presence of the downstream PCI-PCI bridge on the downstream port.
In a general initial configuration, the BIOS of the host must configure all the downstream ports which are not connected to an I/O device.
However, when the downstream PCI-PCI port to which the I/O is not connected is hidden, relative reduction of the initial configuration time is realized.